PCBInside

Prerequisite:

1. A folder which include s-parameter files of capacitors is a library. library must be in your computer. A sample library is here. ☞

2. The capacitor library must be set by Capacitor Explorer. the Capacitor Explorer user guide is here: ☞

Usage:

1. Basic Concept

1.1 PI(Power Integrity)

  PI is keeping power stable to protect wrong operation caused by distorted power. Other words, PI keeps power distorted.

1.2 Source of Distortion(Noise)

  A conductor which connects power source and load is not a perfect one. It’s not ideal. It’s a network containing parasitic resistance, parasitic inductance, and parasitic capacitance. So some of the power is applied to this network and the other is applied to load. The network exists between power source and load is called PDN (Power Distribution Network). That is the reason voltage at load is distorted.

  If the conductor connecting power source and load is a perfect one, the circuit will be like a Fig 1a. But, the real is like a Fig 1b

Consequently,

Vload  =  Vsrc  -  Vpdn

Here, for understanding concept, the arithmetic expression is used.

The amount of noise is related to PDN and dynamic current flowing into load. The condition of dynamic current is defined at Operating Condition section on  this software.

1.3 Power Distribution Network(PDN)

  PDN is composed with R, L, and C.  These values are determined by the physical (geometrical) shape and material characteristics. Therefore power and ground conductor size and the length of gap formed on PCB and the permittivity of dielectric material used in PCB affect the PI.

  You can define R (Resistance of Planes), L (Inductance of Planes), and C (Capacitance of Planes) which are the components of PDN composition at PC Board Structure Definition section  and Load Input Structure Definition section on  this software.

  Because L and C which are the main components of PDN are functions of frequency, the impedance of PDN is changed according to frequency of current flowing into load. 

  If the current flowing through PDN is static, impedance of L will be zero and impedance of C will be unlimited, as a result R will be the only component of PDN. Generally R is very small to ignore. So all supplied voltage from power source will be applied to load. This case is similar to the ideal case. There will be no power distortion.

  But if the current flowing through PDN is dynamic, impedance of L will be increased and impedance of C will be decreased. It seems like that the load supplied by near C not by power source. There will be isolation between load and power source. Under this situation, the current supply can be inappropriate and can make power distortion (noise).

1.4 Power

  The reason power distorted at load is not only PDN but also power source itself. The ideal power can respond all bandwidth of frequency. But real power can respond to a limited bandwidth.

  Fig 2a is an ideal power source and Fig 2b is a real power use in real world. In real power there are inductance component and resistance component inside. Therefore, the more frequency increased, the more responsibility decreased. In other words, the more the frequency of dynamic current required by load is increased, the more impedance of parasitic inductance is increased. As a result power source can’t supply the requisite. This means the power distortion (noise) at load. Consequent, parasitic R, L, and C of power source must be added to PDN. The main impedance components of PDN are C and L of PCB and L of power source.

  You can define parasitics of power source at Power Source Definition section on this software.

1.5 Impedance Graph of PDN

  This graph shows you an impedance characteristic of a PDN. The blue line is a impedance. To 100 KHz, as frequency is increased, the impedance is increased. From 100K Hz to 2 MHz, the impedance is kept 50 mohm. Between 2M ~ 20M Hz, the impedance increased rapidly. After 20M Hz, the impedance is decreased. After showing lowest impedance near 40 MHz, the impedance increase again.

  Assume that 1.8 V is applied to a PDN which impedance characteristic is the same above and 1 A current is flowed through it. If the frequency component of the current is 10K Hz, the impedance of the PDN will be 6 mohm, so the voltage applied to PDN (Vpdn) is 6 mV and the voltage applied to load (Vload) will be 1.794 V. If the frequency component of the current is 1 MHz, the impedance of PDN will be 50 mohm, Vpdn is 50 mV and Vload will be 1.75 V. This value is not 1.8 V but will be no problem to operate. How about 10 MHz? Zpdn will be 0.23 ohm and Vpdn is 0.23 V, as a result, Vload will be 1.57 V. This value is a candidate to fail.  How about 20 MHz? Zpdn will be 3 ohm and Vpdn is 3V. as a result, Vload will be -1.2 V. But this is not possible. Then what will be happen? Cause of high PDN impedance, the current will be reduced. so Vpd will never go high than source and Vload will never be negative. but reduced current make load behave abnormal.

  If supply voltage is 1.8 V and 95% of the supply must be applied to load, Vpdn must be smaller than 0.09 V which is 5% of supply voltage (1.8 V). For this, impedance of PDN must be smaller than 90 mohm acquired by 0.09 V / 1 A. 1 A is the dynamic current value. The red line of above graph is the line under which impedance of PDN kept low for PI. This red line is called target impedance. The above graph let us know that over 6 MHz the voltage ripple at load is bigger than 5% of 1.8 V.

2. Tool Usage

2.1 GUI

2.2 Title Bar

  When you pressed new button or in the beginning, ‘untitled’ is displayed. When a file is loaded or saved, file name is displayed

2.3 Menu

2.4 Power Source Definition Section

  The parasitic components of power source like Rs, Ls, C, E, ESL, ESR are set in power source definition section. These values can be acquired by measuring your power source output at a given load condition. i.e, a specific current consuming condition and comparing the measured data to simulation results. Simulation result can be adjusted for matching the measure one by changing parasitic values.

  There is a circuit which has power source, switch, and load. Refer figure 3. When switch is turned on, voltage waveform like a fig 3 could be acquired. The parasitic inductance(Ls) of power source cause voltage drop when switch is turned on. The inductance could be calculated if you know the ∆t, ∆V, and the amount of current during ∆t. The parasitic resistance(Rs) is the difference voltage between a voltage before switch turned on and a saturated voltage after switch turned on. Using simulator is better to get the C, ESL, and ESR values than calculating by hand.

  If there are many power sources, you can input those all. You can copy current power source information by pressing ‘+’ button. The name of copied power source is ‘new’. You can change the name by clicking it and retype the name and press enter key. A power source which is not needed any more can be deleted by pressing ‘-’ button.

  Change of parasitic values of a power source makes change of the impedance of a PDN at low frequency.

case 1.

case 2.

case 3.

  Compare the case 1 and 2. Reducing  power source intrinsic inductance(Ls) makes the impedance of a PDN lower at low frequency. In other word, Increasing parasitic inductance make impedance higher. Compare the case 1 and 3. Reducing bulk power capacitor makes the impedance of a PDN higher at low frequency.

2.5 PCB Structure Definition Section

  Parasitic inductance and capacitance of PCB make an important role in the impedance of a PDN. The inductance and capacitance components are defined by geometric shape of PCB and material of dielectrics. The parasitic values can be calculated from PCB structure definition panel.

  The parasitic value of capacitance is determined by the area of power and ground conductors and the gap of two conductors. The value of parasitic inductance is determined by the gap and the current flowing path. Generally power and ground conductor has a plane shape for SI (Signal Integrity). Assume the shapes of planes are rectangle. Power plane area is acquired by multiplying horizontal length and vertical length. If power and ground plane is not same, the smaller area must be selected. There is a assumption that power plane area is rectangle. If your design has different shape, use similar rectangle which size is similar. This reduces resistance and inductance extraction tolerance error. You can use s-parameter data to place this section for accurate simulation.

  If there are many PCB definitions, you can input those all. You can copy current PCB definition information by pressing ‘+’ button. The name of copied PCB definition is ‘new’. You can change the name by clicking it and retype the name and press enter key. PCB definition which is not needed any more can be deleted by pressing ‘-’ button.

 The graph below shows the change of PDN impedance according to change of power plane area. Other conditions are same.

case 4.

case 5.

  As power plane area increased, the parasitic capacitance of PDN is increased and resonance frequency of PDN move left. 

2.6 Load Input Structure Definition Section

  Parasitic inductance of Load Input physical structure make an important role in the impedance of a PDN. The inductance components are defined by geometric shape of Power/Ground pin and via of load. The parasitic values can be calculated from load input structure definition panel.

  The parasitic value of inductance at load input pin is determined by the pin and via physical structure. The smaller the size, the smaller the inductance. Low inductance is good for lowering the impedance of a PDN. If the number of power and ground pins increased, the current flowing through a pin or via decreased. Increasing pin number is good for PI. 

If there are many Load definitions, you can input those all. You can copy current load input structure definition information by pressing ‘+’ button. The name of copied load input structure definition is ‘new’. You can change the name by clicking it and retype the name and press enter key. Load input structure definition which is not needed any more can be deleted by pressing ‘-’ button.

 The graph below shows the change of PDN impedance according to change of load input structure. Other conditions are same.

case 6.

case 7.

  As via spacing decreased, the parasitic inductance of power pin decreased. As a result, the impedance  of a PDN at high frequency shift to right.

2.7 Using Bare PCB S-parameter

  For accurate simulation, you can use bare pcb s-parameter data. The data can be acquired by field solver simulator. If you use imported bare PCB data, it will override the definitions of PCB structure and load input structure.

  You can import bare PCB data by right clicking on impedance graph and selecting import bare PCB profile menu.

2.8 Operating Condition Section

  Target Impedance is the maximum limit of a PDN impedance for keeping power ripple within allowed limit. The value is determined by voltage of power source, and tolerance(R), and maximum dynamic current(C).

  Typically IC allows 10% of voltage tolerance. For example, IC operating at 3 V normally allows 2.7 V. But for safety margin at board level, using 2.7 V is very risky. Therefore margin must be smaller. 5% may be adequate. And if this condition is satisfied, voltage will never drop under 2.85 V.

  It is not static current that cause noise but dynamic current. Therefore, when defining maximum dynamic current, it’s not maximum operating current of chips but differential amount of current on operating. If an IC has a current consuming pattern like above fiture, the points inducing noise are current transition point. The current change (∆i) is the value could be maximum dynamic current. 

  The operating frequency and current transition time is related to dynamic current variation, Therefore it will affect the target impedance. 

  The graph below shows the change of operating condition. Other conditions are same.

case 8.

case 9.

  If dynamic current is increased, target impedance must be decreased. 

2.9 Decoupling Capacitor Section

  PDN impedance of a bare PCB is not appropriate in high speed. It has a limited bandwidth. Therefore, decoupling capacitors must be added on PDN to keep impedance low to the frequency you wanted. In empty cell at decoupling capacitors table, right click and select Add menu for adding capacitor. Selecting add menu will show you the decoupling capacitor selection dialog.

  By default the quantity of added capacitor is 1. You can change it by clicking Qty column. The graph below shows the impedance change of a PDN by adding capacitors. The impedance(blue line) is lower than target for all frequency.

  Deleting capacitor listed on decoupling capacitors table can be done by clicking right mouse button on that row at which the capacitor listed and select Delete menu. If you want to edit a decoupling capacitor on table, click right mouse button on the row at which the capacitor listed.

  You can list many decoupling cases by pressing ‘+’ button in the PDN panel. 

  You can see listed capacitors impedance on Capacitor Explorer too by right clicking on table and select view on Capacitor Explorer menu.

  The below show the lunched Capacitor Explorer.

   Compare the upper graph to the below one(PI123).

2.10 Decoupling Capacitor Dialog

  Decoupling capacitor dialog will be appeared when Add or Edit menu is selected on the decoupling capacitors table. In this dialog, you can select a capacitor which will be inserted or replace to a PDN. In here, capacitor mounting condition is defined(left red round rectangle). Mounting inductance is very important factor. It is affected physical structure of PCB stackup, pad, and via. Therefore the value must be set similar to real PCB environment. You can select a capacitor in the capacitor list(upper big blue round rectangle) by clicking. the information of selected capacitor is displayed at selected capacitor characteristics panel(dark yellow round rectangle). The effective inductance of the capacitor which is the sum of mounting inductance and intrinsic capacitor ESL is displayed at right bottom of dialog(right small red round rectangle).

  You can see the impedance graph of selected capacitor by right clicking and selecting view on capacitor explorer menu in capacitor list. 

  By pressing Ok button, capacitor can be listed on decoupling capacitors table.

2.11 Graph

  There are two graphs. The upper graph shows the voltage level at load. The lower graph shows the impedance of a PDN. X axis is frequency. The black line is a voltage level (upper) and a PDN impedance (lower) of bare PCB without decoupling capacitors. The blue line shows decoupling capacitors effect. The red line is the maximum allowed voltage margin (upper) and impedance (lower). Right over the end of red line is not important. 

  The frequency and impedance are displayed in log scale. Minimum displayed voltage is the 70% of supply voltage and the value positioned at 2/3 point is 90% of supply voltage.

  The slide bar under graph can be moved. The ripple voltage value and impedance value of PDN displayed at status bar.

2.13 Status Bar

  Messages related to operation is displayed or ripple voltage and PDN impedance values are displayed.